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Application Note 9855
Functional Descriptions
Voltage Reference
The HI5828 has an internal nominal 1.2V voltage reference
with a ± 10ppm/ o C drift coefficient over the industrial
temperature range. The REFLO pin (18) selects the
reference. Access to pin 18 is provided through solder
jumpers J21 and J22. These jumpers are labeled INT and
EXT for internal or external reference. The REFIO pin (17)
provides access to the internal voltage reference and can be
overdriven if the user wishes to use an external source for the
reference. The internal reference was not designed to drive an
Transformer Output
The evaluation board is con?gured with a transformer output
con?guration, shown in Figure 1. This con?guration was
chosen because it provides: even harmonic performance
improvement due to the complimentary differential signaling;
~12.5 ? R EQ loading to each output of the DAC; drive
impedance of 50 ? for matching with a spectrum analyzer;
and 2x voltage gain. The output of this con?guration will be
biased at zero volts and have an amplitude of ~500mV
(V OUT ) when the DAC is con?gured to drive I OUTFS of
20mA.
external load. Notice that a 0.1 μ F capacitor is placed as close
as possible to the REFIO pin. This capacitor is necessary for
ensuring a noise free reference voltage.
If the user wishes to use an external reference voltage, jumper
J23 must be in place and an external voltage reference
provided via J18, an SMA connector labeled ‘EXT REF’.
Jumper J22 must be soldered so that pin 18 (REFLO) is tied
HI5828
PIN 15 (22)
PIN 16 (21)
50 ?
IOUTA(QOUTA)
100 ?
IOUTB(QOUTB)
50 ?
V OUT = (2 x I OUTFS x R EQ )V
50 ?
SPECTRUM
ANALYZER’S
INPUT
IMPEDANCE
to a logic high (the supply voltage). The recommended limits
of the external reference are between 15mV and 1.2V.
Performance of the converter can be expected to decline as
the reference voltage is reduced due to the reduction in LSB
current size.
If the user wishes to amplitude modulate the DAC, the REFIO
pin can be overdriven with a waveform. The input multiplying
bandwidth of the REFIO input is approximately 1.4MHz when
driving a 100mV signal into the REFIO pin, biased at 0.6V DC .
The 3dB BW reduces as this amplitude is increased. It is
necessary that the multiplying signal be DC offset so that the
minimum and maximum peaks are positive and below 1.2V.
The output current of the converter, IOUTA and IOUTB, is a
function of the voltage reference used and the value of R SET ,
R43.
Output Current
The output current of the device is set by choosing R SET
and V FSADJ such that the resultant of the following equation
is less than 20mA:
I OUT = 32 x V FSADJ /R SET.
REFIO (Pin 17) and FSADJ (Pin 20) of the DAC are the
inputs to an operational ampli?er. The voltage at the FSADJ
pin (V FSADJ ) will be approximately equal to the voltage at
the REFIO pin, which will either be the value of the internal
or external reference. For example, using the internal
reference of (nominal) 1.2V and an R SET value of 1.91k ?
results in an I OUT of approximately 20mA (maximum
allowed). Choose the output loading so that the Output
Voltage Compliance Range is not violated (-0.3 to 1.25V).
The output can be con?gured to drive a load resistor, a
transformer, an operational ampli?er, or any other type of
output con?guration so long as the output voltage
compliance range and the maximum output current are not
violated.
3-2
FIGURE 1.
Sleep
The converter can be put into ‘sleep’ mode by connecting pin
9 of the DAC to either of the converter’s supply voltages. The
sleep pin has an active pull-down current, so the pin can be
left disconnected or be grounded for normal (awake)
operation. On the evaluation board, jumper J15 is provided
for controlling the sleep pin. Remove the solder jumper from
J15 for normal operation and replace it for sleep mode.
Power Supply(s) and Ground(s)
The user can operate from either a single supply or from
dual supplies. The supplies can be at different voltages. It is
important to note that the digital inputs cannot switch more
than 0.3V above the digital supply voltage. The evaluation
board contains two power supply connections, (analog)
AVDD and (digital) DVDD, each with their own ground wire.
Dual ground and power planes is the recommended
con?guration, with the ground planes connected at a single
point (J7 on the evaluation board). Error on the board: the
labels for DGND and AGND are swapped. The DGND label
is next to the analog ground connection and the AGND label
is next to the digital ground connection.
Digital Inputs
The DAC is designed to accept CMOS inputs. The switching
voltage is approximately 1/2 of the digital power supply
voltage, so reducing the power supply can make the DAC
compatible to smaller levels. The digital inputs (data and
clock) cannot go +0.3V higher than the digital supply
voltage, else diode ESD protection can begin to turn on and
performance could be degraded. The clock source can be a
sine wave, with some degradation in performance possible.
The recommended clock is a square wave.
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